Nonlinear classification recognition system

ABSTRACT

In a classification recognition system comprised of a trainable non-linear signal processor having at least one input signal U and one desired output signal Z applied thereto during training and at least one actual output signal X derived therefrom during execution, an improved subsystem is provided for selecting a proper output X according to some predetermined procedure when the processor has identified two or more of the desired output signals Z with the same input signal U during training. Generally, the signal processor stores the desired output signals in registers of a tree-allocated memory array wherein the allocation is determined by a particular input signal U during the training cycle. The subsystem is essentially comprised of an artificial extension of the tree-allocated memory array wherein different values of Z associated with the same input signal U are individually stored during training. In an execution cycle, one or more of such Z&#39;&#39;s may be selected to become the output X for an input U. In one embodiment of the invention only one of such Z&#39;&#39;s is selected according to a predetermined scheme whereby the most likely Z is selected to be the actual output X.

May 7, 1974 NONLINEAR CLASSIFICATION RECOGNITION SYSTEM PrimaryExaminer-Gareth D. Shaw [75] Inventors: William Steele Ewing, Jr.,Dallas; ABSTRACT Thomas Walter Ellis, Richardson; In a classificationrecognition system comprised of a William y Choate, Dallas, 3110ftrainable non-linear signal processor having at least Tex. one inputsignal U and one desired output signal Z ap- [73] Assigneez TexasInstruments Incorporated, plied thereto during training and at least oneactual Dallas, output signal X derived therefrom during execution, animproved subsystem is provided for selecting a [22] Filed: June 1, 1970proper output X according to some predetermined 21 A L N I: 42,428procedure when the processor has identified two or 1 pp 0 more of thedesired output signals Z with the same input signal U during training.Generally, the signal [52] US. Cl. 340/1725 prgcessor tor the desiredoutput signals in registers IIII. CI. of a tree a]l cated memory arraywherein the alloca- FleId of Search tion is determined a particularinput ignal U during the training cycle. The subsystem is essentially[56] Refel'ellfies Cited comprised of an artificial extension of thetree- UNITED STATES PATENTS allocated memory array wherein differentvalues of Z R26,772 1/1970 Lazarus 340/1725 associated with the Sameinput Signal U are individu- 3,446,950 5/1969 King, Jr. et al. 340/1725y Stored during training- In an execution y one 3,333,249 7/1967 Clapper340/1725 or more of such Zs may be selected to become the 3,309,6743/1967 Lemay 340/1725 output X for an input U. In one embodiment of thein- 3,388.38l 6/I968 Prywes t 0/172-5 vention only one of such Zs isselected according to a 314L124 3/1966 Ne-whouse 340/1725 predeterminedscheme whereby the most likely Z is 3,346,844 I0/l967 SCOtt Ct ill v.340/1715 Selected to be the actual Output X. 3,551,895 12/1970 Driscoll,Jr. 340/l72.5

6 Claims, 48 Drawing Figures CHARACTER OPTICAL PREPROCESSOR UIIINONLINEAR IDENTIFICATION READER PROCESSOR- X (1) 1 I l I L J PROCESSINGCONTROL E KNOWN CHARACTER IDENTIFICATION FOR l2 CLOSE FOR I T R AI NI NG 3.810.152 SHEET 03 up 23 KATENTEUW 7 191' X xxx xxx xxXx x x, xxx XXXX XYXX X xxx XXX X XX X xxxx X X x A B CDE L L/NE 0 y 7 1g H.810 l 62SHLU 030? 23 VAL ADP ADE VALZADPZ ADE vAL AD G I @IIVALS ADP D vAL ADPADF vAL ADP e 4 4 4 5 5 Z3 G) J vAL ADP7 624 l fl vAL ADP 6 v 1 "VAL ADPADF vAL ADP ADF vAL ADP e s a s 9 9 9 10 I0 26 J LQ I ROOT LEvEL F/g'7LEAF LEVEL vAL ADPADF N vAL ADP ADF N vAL ADP e A vAL ADP ADF N vAL ADPADF N vAL ADP e A 2 2 I! 4 3 I. 1 s z (D L L 1 I vAL ADPADF N vAL ADP eA l2 2 5- 4 5 2 I Flgl9 Q9 1 vAL ADPADF N vAL ADP ADF N vAL ADP G A -l 23 ll 4 3 l I 3 2 (D L J 1 vALADP ADF N vALADP G A "ATENTEUNAY 7 1971 8 10, 1 62 sum Du or 23 VAL ADP ADF N VAL ADP ADF N I VAL ADP e A -1 2 3 l24 5 2 l 3 z G) l I I LVAL ADP ADF N LVAL ADP e A Fl ll 2 3 4 s 2 VALADPe A 5 5 Z3 I VAL ADP ADF N vALADP ADF N VAL ADP e A 6ll24 |2452 |5Z J lVAL ADP ADF N VAL ADP e A l! 7 3 .l 4 6 Z2 F/g,/2 J I VAL ADP ADF N VALADP e A l3 2 8 l 5 5 2 I y vALADP G A 8 8 Z4 I Q3).

VAL ADP ADF N VAL ADP ADF N VAL ADP e A 2 5 l2 4 5 2 l 3 z,

Q) 1 I G) Y LVAL ADP ADF N VALADP e A ll 7 5 l 4 6 Z l Flgl J I 1 2 LVALADP ADF N 'LVALADP e A l3 9 8 l 5 5 Z3 l l LVAL ADP ADF N VAL ADP s A I52 I0 I 8 .8 24 I @VALADP e A l2 IO Z5 l P TEI] MAY 7 I974 13,81 0. 162

SHEEI 05 HF 23 VAL ADPADF VAL ADP ADF N VAL ADP e A --I I 2 6 I2 4 5 2 I3 2 I (D l I VAL ADP ADF N VAL ADP G A *II 7 3 4 s 2 I vAI ADP ADF NLVAL ADP G A -I3 9 a I 5 I5 Z3 I (D I L VAL ADPADF N VAL ADP G A @3m 2I0 2 a 8 Z4 I \IIALADP e A- I2 Io Z5 I VAL ADP ADF N vAI ADP ADF N VALADP e A -II26-I2452 I3Z|| -VALIADP.ADF N VAL ADP e A IS 7 I0 2 n 4 6 Z2I F/Qa/5 I I VAL ADP ADF N VAL ADP G A l3 9 a II 5 5 2 I (D I I v VALADP ADF N VAL ADP G A -II 2 s I s s 2 I VAL ADP e A I2 Io II -2(ATENTEUMM 7 I91! 13,810,162

sum 11 0F 23 ENTER WITH ID ARRAY 1x VALUES N K(I IDUM=ID(3,IDUM) =I+ITOT I=I+l Figzz FROMIFIG.Z3

F lg, 24

MAX=IAI(I) RETURN MENTEDMY 1 mm Fig 250 Fig. 250

saw 111 OF 23 SHEET 0F 23 Fig, 25b

OR OR 2 c L FF 46 Q J AND "mmum new 3,810,162

SHEEI 17 0F 23 Fig. 250" ATENTEDMAY 7 1974 SHEET 18 0F 23 U wmm 6N 2; S8 2 83 x x x 5 'ATENTED MAY 7 I97,

sum 19 or 23 vb mm weoumn QmN GE Q24 MmN

1. A classification recognition system comprising a trainable signalprocessor having at least one input signal and at least twocorresponding desired output signals applied thereto during training andat least one actual output signal derived therefrom from an input signalduring execution, comprising: a. means for storing all of such two ormore desired output signals identified with the same input signal, b.means for interrogating said processor during execution with an inputsignal, means responsive to the interrogation for defining two or morecorresponding desired output signals corresponding to said input signal,said input signal having at least two corresponding desired outputsignals stored in said storage means, and c. means responsive to saidinterrogation means for selecting one or more of such desired outputsignals as the actual output of the system.
 2. The classificationrecognition system of claim 1 wherein said selection means selects theentire set of all desired output signals identified with said same inputsignal as the actual output of the system.
 3. The classificationrecognition system of claim 2 including means responsive to said storingmeans for accumulating and storing the number of occurrences that eachof such two or more desired output signals was identified with said sameinput signal.
 4. The classification recognition system of claim 3including means for periodically rearranging in said processor the setof all desired output signals identified with said same input signal inthe order of their occurrences whereby the desired output with the mostoccurrences comes earliest in the set.
 5. A classification recognitionsystem comprising a trainable signal processor having at least one inputsignal and at least one corresponding desired output signal appliedthereto during training, and at least one actual output signal derivedtherefrom from an input signal during execution, a tree-allocated memoryarray, said input signal during training defining a path through thelevels of said tree-allocated memory array, said corresponding desiredoutput being stored at the leaf level of said tree-allocated memoryarray, said processor capable of identifying two or more desired outputsignals corresponding to the same input signal, a. an additional levelof said tree-allocated memory array extending from a path beyond andthrough said normal leaf level for storing all such two or more desiredoutput signals identified with the same input signal, b. means forinterrogating said processor during execution with an input signal, saidinput signal having at least two corresponding desired actual outputsignals stored in said additional level of said tree-allocated memoryarray, and c. means responsive to said interrogating means for selectinga set of one or more of such desired outputs stored in such additionallevel as the actual output of the system.
 6. A classificationrecognition system comprising a trainable signal processor having atleast one input signal and at least one corresponding desired outputsignal applied thereto during training and at least one actual outputsignal derived therefrom from an input signal during executioncomprising: a. means for encoding said input signal into a plurality ofkey components, b. a tree-allocated memory array having a plurality oflevels including leaf levels corresponding to said plurality of keycomponents as encoded by said encoding means, said key componentsdefining a path through the levels of said memory array normallyterminating at a leaf level, the leaf levels of said tree-allocatedmemory array having means for storing one desired output correspondingto an input signal during training, c. at least one additional level ofsaid tree-allocated storage array extending from a path through andbeyond one of said leaf levels for storing all desired output signalsidentified with a same set of key components when two or more desiredoutput signals have been identified with a same set of key componentsduring training, d. said leaf level including means for indicating theexistence of such additional level extending from said leaf level, e.means for sequentially comparing the key components of an input signalduring execution with the key components defining paths through thelevels of said tree-allocated memory array, f. firsT means responsive tosaid comparison means for selecting the desired output stored at a leaflevel of said tree-allocated memory array as the actual outputcorresponding to the input signal during execution of the system whenthere is no additional level extending from the leaf level of a pathdefined by the key components of the input signal during execution, andg. second means responsive to said comparison means for selecting a setof one or more desired output signals stored in the additional level asthe actual output of the system corresponding to the input signal whenthere is such an additional level extending from the leaf level of apath defined by the key components of an input signal during execution.